As solid-state imaging devices (image sensors) using photoelectric conversion elements which detect light to generate electric charges, CMOS (complementary metal oxide semiconductor) image sensors have been put into practical use. CMOS image sensors are being widely applied as parts of digital cameras, video cameras, monitoring cameras, medical endoscopes, personal computers (PC), mobile phones, and other portable terminal devices (mobile devices) and various other types of electronic apparatuses.
A CMOS image sensor has a floating diffusion (FD) amplifier having, for each pixel, a photodiode (photoelectric conversion element) and floating diffusion layer. For readout, the mainstream type is the column parallel output type that selects a certain row in a pixel array and simultaneously reads the pixels out to a column output direction.
In this regard, in a CMOS image sensor, photo charges which are generated and stored in the photodiodes are sequentially scanned and read out for each of the pixels or each of the rows. When performing this sequential scanning, that is when employing a rolling shutter as an electronic shutter, the start times and end times of exposure for storing photo charges cannot be made to match in all of the pixels. For this reason, in the case of sequential scanning, when capturing an image of a moving subject, there is the problem of occurrence of distortion in a captured image.
Therefore, in capturing an image of a subject moving at a high speed or in sensing applications requiring simultaneity of the captured image where image distortion is not allowed, as the electronic shutter, a global shutter which starts the exposure and ends the exposure at the same timing for all pixels in the pixel array portion is employed.
In a CMOS image sensor employing a global shutter as the electronic shutter, a pixel is, for example, provided with a signal holding part which holds a signal read out from a photoelectric conversion reading part in a signal holding capacitor. In a CMOS image sensor employing a global shutter, simultaneity of the entire image is secured by storing the charges of the photodiodes as voltage signals all together in the signal holding capacitors in the signal holding parts and later sequentially reading them out (see for example NPLT 1). Further, this CMOS image sensor has bypass switches for bypassing the signal holding parts and transferring the outputs of the photoelectric conversion reading parts to signal lines and therefore is configured so as to have a rolling shutter function in addition to a global shutter function.
FIG. 1 is a circuit diagram showing a conventional example of a pixel of a CMOS image sensor employing a global shutter.
A pixel 1 in FIG. 1 includes a photoelectric conversion reading part 2 and a signal holding part 3.
The photoelectric conversion reading part 2 in FIG. 1 includes a photodiode (photoelectric conversion element) and pixel amplifier. The photoelectric conversion reading part 2 has a transfer transistor tg1-Tr, a reset transistor rst1-Tr, a source-follower transistor sf1-Tr, and an output node nd1 with respect to a photoelectric conversion element comprised of a photodiode PD1. The output node nd1 is formed by a source side of the source-follower transistor sf1-Tr. At a gate of the source-follower transistor sf1-Tr, a floating diffusion FD1 is connected.
A signal line lsgn1 between this output node nd1 and the input part of the signal holding part 3 is for example driven by a constant current source I1 arranged at the input part of the signal holding part 3. The source-follower transistor sf1-Tr outputs the readout signal (VSIG) and the read out reset signal (VRST) of the column output, which is obtained by converting the charge in the floating diffusion FD1 to a voltage signal corresponding to the charge amount (potential), to the output node nd1.
The signal holding part 3 of the pixel 1 basically includes an input part 3-1 to which the current source I1 famed by a bypass transistor bs1-Tr is connected, a sample-and-hold part 3-2, an output part 3-3, and nodes nd2 to nd4.
The sample-and-hold part 3-2 has a switch element SW1 which selectively connects the signal holding capacitor of the sample-and-hold part 3-2 with the output node nd1 of the photoelectric conversion reading part 2 of the pixel 1 in the global shutter period, signal holding capacitors C1 and C2 capable of holding the signal output from the output node nd1 of the photoelectric conversion reading part 2 of the pixel 1, and a reset transistor rst3-Tr. The switch element SW1 is connected between the node nd2 and the node nd3 connected to the sample-and-hold part 3-2. The switch element SW1 becomes conductive in for example a period where a signal SH is a high level (H level). The signal holding capacitor C1 is connected between the node nd3 and node nd4. The signal holding capacitor C2 is connected between the node nd4 and a reference potential VSS.
The reset transistor rst3-Tr is connected between a power supply line Vdd of a power supply voltage VDD and controlled by a control signal rst3 supplied to a gate through a control line. The reset transistor rst3-Tr is selected and becomes a conductive state in a reset period where the control signal rst3 is the H level and resets the node nd4 (and capacitors C1 and c2) to the potential of the power supply line of the power supply voltage VDD.
The output part 3-3 includes a source-follower transistor sf3-Tr which outputs signals held in the signal holding capacitors C1 and C2 in accordance with the held voltage in the global shutter period and selectively outputs the held signals through the selection transistor sel3-Tr to the vertical signal line LSGN1 driven by the constant current source.
The source-follower transistor sf3-Tr and the selection transistor sel3-Tr are connected in series between the power supply line Vdd and the vertical signal line LSGN1.
A gate of the source-follower transistor sf3-Tr is connected to the node nd4. The selection transistor sel3-Tr is controlled by a control signal sel3 supplied to the gate through a control line. The selection transistor sel3-Tr is selected and becomes a conductive state in the selection period where the control signal sel3 is the H level. Due to this, the source-follower transistor sf3-Tr outputs the readout voltage (VRST, VSIG) of the column output in accordance with the held voltages of the signal holding capacitors C1 and C2 to the vertical signal line LSGN1.
The stacked type CMOS image sensor disclosed in NPLT 1 has a stacked structure of a first substrate (pixel die) and a second substrate (ASIC die) connected through microbumps (connecting parts). Further, the photoelectric conversion reading parts of the pixels are formed on the first substrate, while the signal holding parts of the pixels, signal lines, vertical scanning circuit, horizontal scanning circuit, column readout circuit, and so on are formed on the second substrate.